1. Field of the Invention
The invention relates to a buffer circuit, and more particularly, relates to an analog output buffer of a D-A converter (digital-to-analog converter). The invention is suitable to an output buffer used in a liquid crystal display device, and especially, suitable to an output buffer made on a glass substrate of the liquid crystal display device through the same process for LCDs using the low temperature polysilicon (LTPS) technology.
2. Description of the Prior Art
A conventional analog buffer circuit, connected to an output terminal of a D-A converter, has a well known arrangement comprising a three-stage inverter amplifier (inverting amplifier) built up by means of capacitive coupling and negative feedback path, as shown in a circuit diagram in FIG. 7.
Throughout the accompanying drawings, a gate terminal accompanied with a small circle represents a P channel MOS transistor.
The analog buffer circuit comprises a first inverter having a P channel MOS (PMOS) transistor PT1 and an N channel MOS (NMOS) transistor NT1 connected in series between a supply voltage VDD and a ground VSS, a second inverter similarly having PMOS transistor PT2 and NMOS transistor NT2 connected in series, and a third inverter having PMOS transistor PT3 and NMOS transistor NT3 connected in series. A common gate node of the transistors PT1 and NT1 is connected to an input terminal via a capacitor C1, and a first switch SW1 is provided between a connection node NI of the transistors PT1/NT1 and their common gate node.
Similarly, a capacitor C3 is connected between the connection node N1 and the common gate node of the transistors PT2 and NT2. A second switch SW2 is provided between the common gate node of the transistors PT2/NT2 and a connection node N2 of the transistors PT2 and NT2.
In addition, a capacitor C4 is connected between the connection node N2 and a common gate node of the transistors PT3 and NT3. A third switch SW3 is provided between the common gate node of the transistors PT3/NT3 and a connection node N3 of the transistors PT3 and NT3. The connection node N3 serves as an output node VOUT.
A terminal opposing the input terminal of the capacitor C1 is coupled to the connection node N3 via the capacitor C2 and a fourth switch SW4 to form a negative feedback path, and a reference voltage Vref is applied to a connection node of the capacitor C2 and the switch SW4 via a switch SW5.
Thus, this analogue buffer circuit is configured such that three stages of inverters are coupled through a capacitive element and a negative feedback path.
An operation of this circuit will now be described.
First, in a standby mode (referred to also as “setup mode”) where the initializing and the standby operation are carried out, the switches SW1, SW2, SW3 and SW5 are turned on, and the switch SW4 is turned off. This permits the reference voltage Vref to be applied to charge the capacitors C2, C3 and C4.
Next, in an active mode where the circuit serves as a buffer, the switches SW1, SW2, SW3 and SW5 are turned off, and the switch SW4 is turned on. Thereby, the transistors are driven in response to the input voltage VIN to transfer an inverted signal from one inverter stage to another and resultantly produce an inverted output to the output terminal VOUT.
FIG. 8 is a circuit diagram showing another example of conventional analog buffer circuit. As mentioned later, this circuit is disclosed in Non-Patent Document 1 listed below.
The buffer circuit comprises roughly three main components.
First, the first main component is a current source circuit having four transistors PT11, PT12, NT12 and NT11 connected in series between a supply voltage VDD and a ground VSS. Gate and drain of the transistor PT11 are connected together and source of the transistor PT11 is connected to the supply voltage VDD. Source, gate and drain of the transistor PT12 are respectively connected to the drain of the transistor PT11, the ground VSS and drain of the transistor NT12. Gate and source of the transistor NT12 are respectively connected the supply voltage VDD and drain of the transistor NT11. Source and gate of the transistor NT11 are respectively connected to the ground VSS and the drain of the transistor NT11.
The current source circuit generates current I1.
Next, the second main component is an operational amplifier (OP amp). The operational amplifier comprises first and second amplifiers. In the first amplifier, gate and source of a bias transistor PT21 are respectively connected to the transistor PT11 of the current source circuit and the supply voltage VDD. Drain of the bias transistor PT21 is connected to sources of two differential transistors PT22 and PT23. Drains of the transistors PT22 and PT23 are respectively connected to drains of transistors NT21 and NT22, wherein the gates are commonly connected. Any of the transistors NT21 and NT22 may have a grounded source, and function as a load transistor.
The second amplifier is configured symmetrical to the first amplifier described above.
In the second amplifier, the drain of the bias transistor NT33 is connected to sources of two differential transistors NT31 and NT32. Drains of the transistors NT31 and NT32 are respectively connected to drains of two load transistors PT31 and PT32, wherein the gates are commonly connected. Any of the load transistors PT31 and PT32 may have a connected source to the supply voltage VDD.
Input voltage VIN is applied to the gates of the transistors PT23 and NT31. In addition, the remaining transistors of the pairs of the differential transistors, namely, the transistors PT22 and NT32, have respective gates connected to a connection node N10 or an output terminal VOUT.
The third main component comprises a P channel transistor PT41, wherein the drain and source are respectively connected to the connection node N10 and the supply voltage VDD, and an N channel transistor NT41, wherein the drain and source are respectively connected to the connection node N10 and the ground VSS, whereby together, the transistors form an inverting circuit. The output from the right hand side amplifier is connected to a gate of the transistor PT41 while the output from the left hand side amplifier is connected to the gate of the transistor NT41.
In this circuit, the operational amplifier is stably driven using the current source, and hence, any single stage of the inverting circuits can produce a stable buffer output.